Abstract:
A general purpose CCD controller that can address any CCD, has been developed at the Indian Institute of Astrophysics. It is based on a Digital Signal Processor (DSP) chip, Motorola DSP 56002 for implementing essential operations such as read-out of the CCD, interfacing with the host and correlated double sampling for reset noise elimination. In order to reduce the chip count and size of the controller with a view to adopt it for building a space borne application of the camera, a need has been felt to implement the design with the use of a Field Programmable Gate Array (FPGA) approach. Such an approach would not only be efficient but would also be able to enhance the image processing strategies. After examining the functionality of the DSP board, Bias and Clock board, Host Interface and Data Acquisition functions, an Algorithmic State Machine (ASM) is derived from the DSP code. In this paper we report the ASM design that has been used to design the system using the Hardware Description Language (HDL). Verilog HDL is used to create the code, which can be tested and debugged using Xlinx ISE software package. This paper also reports the timing generator that has been implemented on Xlinx chip. It is proposed to implement the serial and parallel communication with fibre optics link in this approach.
